The present invention relates to solar cells formed on a semiconductor substrate.
State of the art high efficiency photo voltaic (“PV”) solar cells have been introduced as a component in a die (chip) or wafer. A typical solar cell producer uses semiconductor manufacturing processes that are specialized to produce the PV solar cells. The same producer sells the solar cells in the form of chips or wafers. Each solar cell is formed on a single chip or wafer. The buyer of these cells then assembles them in large panels in a series or series-and-parallel combination to produce a higher output power than is possible from one monolithic solar cell.
A solar cell, in its basic form, is a p/n junction (a diode) that generates 0.4-0.7 volts when light shines on it. The high efficiency cells produce the higher voltage range, which is about 0.65v to 0.7v. Accordingly, a user of these cells generally has to connect them in series to generate a higher, more useful voltage. A plurality of such solar cell arrays are connected in parallel to produce higher output current, thereby generating higher electrical power.
For a 6 volt output, 10 PV cells are generally connected in series. Each chip has to be isolated from each other and connected in a scheme, as shown in FIG. 1A, where solar cells PV1 to PV10 are connected in series. The potential of a node 1 is about 6 volts above that of a node 20.
FIG. 1B shows a die bonding and mounting on a substrate 80, where the PV chips are 41-50, representing 10 PV cells, are connected in series. FIG. 1B illustrates a component configuration corresponding to FIG. 1A. The connections are done via conducting wires 61-71. The dice are mounted on conductor pads 21-30. As shown, many additional components (e.g., the connecting wires, conductor pads, and substrate) are needed to place the solar cells in series and obtain a higher voltage output. This results in increased material and labor costs.
One proposed solution has been to use a dielectric isolation (DI) technology. This technology provides a monolithic chip or substrate having a higher voltage output without using connecting wires, conductor pads, and other external components. The DI technology may be used to provide a monolithic substrate having a plurality of solar cells. At first, a photoresist layer is provided on a front side of a silicon substrate. The photoresist is patterned and etched to expose certain parts of the silicon substrate. The exposed parts are etched to form a plurality of grooves on the substrate. The photoresist is then removed.
The substrate is doped with impurities to form a buried layer. An oxide layer is formed on the buried layer. A polysilicon layer is deposited on the oxide layer to a thickness of 500 microns or more. The substrate is then flipped over and grinded to remove excess portions of silicon substrate on the backside.
The DI technology is costly and is generally considered to be impractical. This technology, as explained above, requires deposition of a thick layer of polysilicon and then mechanical coarse grinding techniques, which is both costly and results in a high degree of defects. Also, it is difficult to make a small-sized solar cell devices using the DI technology due to its coarse grinding step.